Sandy Choj vs Nehalem Architecture
Sandy Choj thiab Nehalem Architectures yog ob ntawm cov txheej txheem tshiab tshaj plaws microarchitectures qhia los ntawm Intel. Nehalem processor architecture raug tso tawm hauv 2008 thiab yog tus ua tiav rau Core microarchitecture. Sandy Bridge processor microarchitecture yog tus ua tiav rau Nehalem microarchitecture thiab nws tau tso tawm hauv 2011. Pom tseeb, yog qhov kev tso tawm tom qab, Sandy Bridge muaj kev txhim kho ntawm cov yam ntxwv thiab kev ua tau zoo los ntawm Nehalem architecture.
Nehalem Architecture
Nehalem processor architecture tau tso tawm xyoo 2008 thiab yog tus ua tiav rau Core microarchitecture.45 nm raug siv rau Nehalem architecture. Thaum lub Kaum Ib Hlis 2008 Intel tau tshaj tawm lawv thawj processor tsim siv Nehalem processor microarchitecture thiab nws yog Core i7. Ob peb lwm Xeon processors, i3 thiab i7 sai sai ua raws. Apple Mac Pro chaw ua haujlwm yog thawj lub khoos phis tawj uas suav nrog Xeon processor (raws li Nehalem). Thaum lub Cuaj Hlis 2009, thawj Nehalem architecture raws li mobile processor tau tso tawm. Nehalem processor architecture reintroduced hyperthreading thiab L3 cache (txog 12MB, sib koom los ntawm tag nrho cov cores), uas tau ploj lawm hauv Core-based processors. Nehalem processor tuaj hauv 2, 4 lossis 8 cores. Lwm cov yam ntxwv tseem ceeb tam sim no nyob rau hauv Nehalem microprocessors yog DDR3 SDRAM lossis DIMM2 lub cim xeeb tswj, Kev sib xyaw ua ke Graphics Processor (IGP), PCI thiab DMI kev koom ua ke rau lub processor, 64 KB L1, 256 KB L2 caches, theem ob ceg kwv yees thiab kev txhais lus tsis zoo.
Sandy Bridge Architecture
Sandy Choj processor architecture yog tus ua tiav rau Nehalem architecture tau hais los saum toj no. Sandy Choj yog ua raws li 32 nm kev tsim khoom. Thawj cov txheej txheem raws li cov qauv no tau tso tawm thaum Lub Ib Hlis 9, 2011. Zoo ib yam li Nehalem, Sandy Bridge siv 64KB L1 cache, 256 L2 cache thiab sib koom L3 cache. Kev txhim kho ntawm Nehalem yog nws txoj kev ua haujlwm zoo tshaj plaws ntawm kev kwv yees, kev yooj yim rau kev ua lej lej, kev txhawb nqa encryption ntawm AES nrog thiab SHA-1 hashing. Tsis tas li ntawd, cov txheej txheem qhia txhawb nqa 256-ntsis wider vectors rau floating-point arithmetic hu ua Advanced Vector Extensions (AVX) yog qhia hauv Sandy Bridge processors. Nws tau pom tias Sandy Bridge processors muab txog li 17% nce CPU kev ua tau zoo piv rau Lynnfield processors raws li Nehalem architecture.
Qhov txawv ntawm Sandy Choj thiab Nehalem Architecture
Sandy Bridge architecture tso tawm xyoo 2011 yog tus ua tiav rau Nehalem processor microarchitecture, uas tau tso tawm xyoo 2008. Nkag siab, Cov Txheej Txheem raws li Sandy Bridge architecture muaj ntau qhov kev txhim kho ntawm cov txheej txheem raws li Nehalem Architecture. Qhov txawv ntawm qhov tshwj xeeb yog Sandy Choj siv lub tshuab nm me me rau nws cov circuitry. Kev ua tau zoo, nws tau lees tias muaj 17% kev txhim kho nyob rau hauv cov nqe lus ntawm ib-teev hauv paus hauv Sandy Bridge processors dua Nehalem processors. Sandy Choj tau txhim kho cov ceg twv ua ntej, cov chaw ua lej transcendental, AES rau encryption, SHA-1 rau hashing thiab Advanced Vector Extension rau kev txhim kho floating-point lej lej. Nyob rau hauv kev tshawb fawb benchmark ua los ntawm SiSoftware ntawm 3066MHz, 4 core Nehalem processor thiab 3000MHz, 4 core Sandy Choj processor, nws tau pom tias yav tas los ua tau zoo dua qub hauv thaj tsam ntawm CPU lej, CPU multimedia, Multi-core efficiency, Cryptography thiab zog efficiency. Tsis tas li ntawd, nyob rau hauv thaj chaw ntawm Media transcoding, Memory maub los ceev thiab L3 cache kev ua tau zoo, Sandy Bridge processor yeej kev sib ntaus sib tua ntawm Nehalem processor.
